1. Field of the Invention
The present invention relates to a CRC operational system for use in detection of a communication error or the like.
2. Description of the Related Art
An example of a network system for transmitting such data as text, voice or video in the form of a packet is shown in FIG. 2. The network of the drawing includes multiplex lines 1, packet exchanges 2A, 2B and 2C, packet terminals 3A to 3C, exchanges 4A to 4C, and telephone sets 5. When voice data is entered, for example, into the packet terminal 3A, the voice data is converted into coded data, resolved into predetermined units of division data and again assembled into a packet having such header data as party designation data attached thereto at the terminal 3A. The thus-obtained packet is transmitted from the terminal 3A through the packet exchanges 2A and 2B to the party packet terminal 3B.
FIG. 3 shows a data format of a packet 10 on the multiplex line 1. In the drawing, a header data field 11 contains data indicative of a route leading to a party destination and the party destination, and a header CRC field 12 contains a check sequence (CRC code) for checking for the header data field 11 (whether there is an error in the field 11). The header data field 11 and the header CRC field 12 make up a header part 13. As will be appreciated from this explanation, the header CRC field 12 operates only the header data field 11. The header part 13 and a data part 14 make up the packet 10.
On the multiplex line 1, a frame prescribed by the multiplex line 1 is used for transmitting data. For transmitting the fixed-length packet 10, however, a part of the frame other than the parts for a frame synchronization pattern and line maintenance data is used. Since the lengths of the above frame synchronization pattern and line maintenance data generally do not satisfy an integer multiple relationship with the length of the fixed-length packet, it is necessary to detect the position of the packet independently of the frame synchronization.
As one of methods for detecting the packet position, there has been suggested a method which performs a CRC check for a header part and when the check result (syndrome) is zero, determines a position of a packet from which the CRC check started to be a header position of the packet.
FIGS. 4 and 5 show a prior art CRC generation circuit 20 and a prior art CRC check circuit 30 when a polynomial G(X)=X.sup.3 +X+1 is generated respectively (4 bits of message, 3 bits of check sequence).
The CRC generation circuit 20 of FIG. 4 comprises delay elements 21, 22 and 23, logical exclusive "OR" circuits 24 and 25, and switches S.sub.1 and S.sub.2. In the CRC generation circuit 20, when the circuit 20 outputs an input sequence without any modification, the switch S.sub.1 is switched to its B side and the switch S.sub.2 is switched to its feedback side (connected to the exclusive circuits 24 and 25). In the CRC generation circuit 20 when generating and outputting a CRC code, the switch S.sub.1 is set to its A side while the switch S.sub.2 is set to its 0 input side (ground side).
Meanwhile, the CRC check circuit 30 of FIG. 5 comprises delay elements 31, 32 and 33, logical exclusive "OR" circuits 34 and 35, an error check circuit 36, and a group of delay elements 37. The CRC check circuit 30 computes CRC on the basis of a received sequence and-checks whether or not the computed CRC coincides with the received CRC. When a coincidence is found between the computed and received CRCs, the delay elements 31, 32 and 33 have statuses of "0", "0" and "0" respectively. The error detector 36 detects the statuses of the delay elements 31, 32 and 33 and when detecting the statuses of the delay elements 31, 32 and 33 other than "0, 0, 0", externally outputs an error detection signal. In such an error detection mode, the CRC check circuit 30 performs such processing as discarding of the received sequence. In this connection, the received sequence is output as delayed by a time corresponding to 8 bit line clocks, since the received sequence is to be discarded when the group of delay elements 37 detect an error.
For the convenience of explanation, it is assumed hereinafter that the above CRC circuit 20 is used to compute the header CRC 12 of a packet. In the above case, when the computed CRC is expressed in terms of (code length, message length), it is (7 codes, 4 codes).
A flow of packets is shown as an example in FIG. 6. If the syndrome of the CRC check is zero then the CRC-computation starting position is set as the head of the packet, as mentioned above. The CRC check circuit of the receiver side, before computing the CRC, initializes its interior contents (clears the interior contents to zero), and after having received the header part, outputs the syndrome. In other words, one syndrome computation, in this case, requires a time corresponding to 7 bit line clocks, during which the CRC check circuit of the receiver side is occupied by a series of syndrome computation. This means that, when the syndrome is not zero at the current bit position from which the computation starts, a bit position to be next checked corresponds to a position shifted by 8 bits. For this reason, the hunting process for detecting a correct packet position becomes long, thus disadvantageously requiring a lot of time for packet synchronization.
For the purpose of eliminating the above problem, such an arrangement as to provide a plurality of syndrome computation circuits are considered. This however involves another problem that the circuit scale is made large.
As mentioned above, the prior art CRC operational system has had such a problem that, since a considerable amount of bit clock time is used only for a series of syndrome computations, the hunting process necessary for detecting the header position of a packet is made long and thus a synchronization return time is made long.